1. Field of the Invention
Embodiments of the invention disclosed herein relate to integrated circuits synchronized with clocks. In particular, embodiments of the invention disclosed herein relate to integrated circuits including controllers capable of correcting clock skews.
2. Description of the Related Art
Semiconductor integrated circuits generally include many electronic device components such as transistors, diodes, inverters, and so on. Those electronic components are operatively interconnected with each other to constitute structures (e.g., gates, cells, memory units, operation units, controllers, decoders, and so on) of large scale circuits. Integrated circuits also include a plurality of conductive layers, such as metal and/or polysilicon lines, for interconnecting the electronic devices and circuit components.
For reliable operations of the integrated circuits, all the electronic devices and circuit components should be operable in sync with each other. Clock signals are used for synchronizing the electronic devices and circuit components. Typically, clock signals are oscillating signals, which are required to have very small skews so as to maintain synchronization among various circuit components. However, even if a plurality of different circuits are connected to a same clock source, characteristics of clock distribution lines, e.g., length of clock distribution line, may cause a clock skew.
With developments of semiconductor technology, operating frequencies of microprocessors are becoming higher, and thus, managing clock skew is more important. For the purpose of lessening troubles of clock skews, most integrated circuits employ special clock distribution networks. A mesh-type clock network may be helpful in reducing a clock skew, but such a network may dissipate a relatively high amount of power. Thus, in some cases, a plurality of clock meshes are employed.
However, in a distribution network structure including a plurality of clock meshes, while the clock skew may be very small in each mesh, there may be problems due to an imbalance of the clock skews between or among the plurality of clock meshes.